1. Field of the Invention
The present invention relates to a microprocessor, and more specifically to a controller for a cache memory incorporated in the microprocessor.
2. Description of Related Art
At present, most microcomputers have a high speed memory called a "cache memory" (simply called a "cache" hereinafter) in addition to the usual (external) main memory and secondary memories. In general, the access speed to the main memory is very slow, for example a few tenths to a few hundredths of the internal processing speed of a microprocessor or central processing unit (CPU), and therefore, if the microprocessor fetches necessary programs and data from the main memory at each execution of an instruction, the operation speed of the microprocessor is limited by the access speed of the main memory. In other words, high speed processing cannot be expected. For solving this problem, the cache has been proposed and is widely used at present. The cache copies a portion of the programs and data that are stored in the main memory and that are most heavily used, and in the operation of the microcomputer, the microprocessor accesses the cache (i.e., high speed access memory) internally provided in the microcomputer in place of accessing the external main memory, so that the microprocessor can execute the operation at a high speed.
In a cache associated to a microprocessor, hitherto, an address signal from the microprocessor is preferably directly supplied to the cache in order to make as short as possible a time from the moment the address signal is outputted from the microprocessor to the moment there is discriminated whether or not the cache is hit. However, some microprocessors are adapted such that when the microprocessor is in a RESET condition, in an INTERRUPT condition or in a BUS HOLD condition, output terminals of the microprocessor are put in a high impedance condition. If the output signals of this type of microprocessor are directly coupled to the cache as mentioned above, an intermediate level propagation will occur, so that inputs of the cache become logically unstable.
In order to overcome the above drawback, it has been proposed to pull up the signal lines from the microprocessor to the cache, so that when an input signal will not been put in the high impedance condition. However, pull-up resistors and their associated connection lines for the pull-up purpose will inevitably induce a floating or parasitic capacitance, which will cause a delay in signal propagation. This delay will often give rise to a significant adverse influence on the timing of an operation of cache controller.